Publications

2024

1. IEEE

   A 7.5-GHz Subharmonic Injection-Locked Clock Multiplier Featuring a 120 \times Multiplying Factor and 92.3-fs RMS Jitter Including Reference Spur

   Hangil Choi, and SeongHwan Cho

   IEEE Journal of Solid-State Circuits, 2024

   DOI Bib

   @article{10702551,
     author = {Choi, Hangil and Cho, SeongHwan},
     journal = {IEEE Journal of Solid-State Circuits},
     title = {A 7.5-GHz Subharmonic Injection-Locked Clock Multiplier Featuring a 120 $\times$  Multiplying Factor and 92.3-fs RMS Jitter Including Reference Spur},
     year = {2024},
     volume = {},
     number = {},
     pages = {1-10},
     keywords = {Voltage-controlled oscillators;Clocks;Calibration;Jitter;Timing;Switches;Phase locked loops;Time-frequency analysis;Phase noise;Phase distortion;Frequency synthesizer;low-jitter;low-reference spur;phase-locked loop (PLL);subharmonic injection-locked clock multiplier (SILCM);voltage-controlled oscillator (VCO)},
     doi = {10.1109/JSSC.2024.3465436}
   }

2. IEEE

   19.1 A 7.5GHz Subharmonic Injection-Locked Clock Multiplier with a 62.5MHz Reference, -259.7dB FoMJ, and -56.6dBc Reference Spur

   Hangil Choi, and SeongHwan Cho

   In 2024 IEEE International Solid-State Circuits Conference (ISSCC), 2024

   DOI Bib

   @inproceedings{10454375,
     author = {Choi, Hangil and Cho, SeongHwan},
     booktitle = {2024 IEEE International Solid-State Circuits Conference (ISSCC)},
     title = {19.1 A 7.5GHz Subharmonic Injection-Locked Clock Multiplier with a 62.5MHz Reference, -259.7dB FoMJ, and -56.6dBc Reference Spur},
     year = {2024},
     volume = {67},
     number = {},
     pages = {348-350},
     keywords = {Phase noise;Ring oscillators;Limiting;Voltage-controlled oscillators;Timing;Solid state circuits;Phase locked loops},
     doi = {10.1109/ISSCC49657.2024.10454375}
   }

2023

1. KJKIEES

   Evaluation and Analysis of High Temperature Characteristics of 94 GHz SiGe BiCMOS PLL

   Sang-Heung Lee, Han-Gil Choi, Ju-Ho Lee, and 2 more authors

   The Journal of Korean Institute of Electromagnetic Engineering and Science, 2023

   Abs DOI Bib

   In this study, a 94 GHz PLL chip was designed using the integer-N PLL structure, and the results of a high-temperature test for the chip are discussed. The 94 GHz PLL was designed to exhibit a phase noise of −90 dBc/Hz or less at a 1 MHz offset frequency using a 0.13 μm SiGe BiCMOS process. In addition, a high-temperature test of the MIL-STD-331C standard was conducted on a manufactured 94 GHz SiGe PLL chip mounted on a test board. As a result of the test, the chip total current change before and after the high-temperature test was 4.7 %, and the phase noise changes of both 94 GHz VCO and PLL were 2.3 dB. These results confirm that, even after the high-temperature test, the flattening of the low-frequency noise was well maintained because the VCO noise was filtered by the PLL.

   @article{10.5515/KJKIEES.2023.34.10.743,
     author = {Lee, Sang-Heung and Choi, Han-Gil and Lee, Ju-Ho and Jung, Kyu-Chae and Cho, Seong-Hwan},
     journal = {The Journal of Korean Institute of Electromagnetic Engineering and Science},
     publisher = {The Korean Institute of Electromagnetic Engineering and Science},
     title = {Evaluation and Analysis of High Temperature Characteristics of 94 GHz SiGe BiCMOS PLL},
     year = {2023},
     volume = {34},
     number = {10},
     url = {https://doi.org/10.5515/KJKIEES.2023.34.10.743},
     pages = {743-746},
     doi = {10.5515/KJKIEES.2023.34.10.743}
   }

2022

1. J-STAGE

   Technique for fast triangular chirp modulation in FMCW PLL

   Han Gil Choi, Sang Heung Lee, and Seong Hwan Cho

   IEICE Electronics Express, 2022

   DOI Bib

   @article{Han Gil Choi202219.20220214,
     title = {Technique for fast triangular chirp modulation in FMCW PLL},
     author = {Choi, Han Gil and Lee, Sang Heung and Cho, Seong Hwan},
     journal = {IEICE Electronics Express},
     volume = {19},
     number = {14},
     pages = {20220214-20220214},
     year = {2022},
     doi = {10.1587/elex.19.20220214}
   }